As the dimensions of transistor devices continue to shrink, various issues arise imposing increasing demands for methodology enabling the fabrication of semiconductor devices having good lithographic printability. Smaller transistors allow more transistors to be placed on a single substrate, thereby allowing relatively large circuit systems to be incorporated on a single, relatively small die area. A sidewall image transfer (SIT) process for defining gates for fin-shaped field effect transistors produces transistors with smaller channel lengths and a smaller gate pitch, which exhibit higher current drive strength and less capacitance, and can operate at higher frequency, thus providing overall increased device performance. However, smaller transistors require reduced feature sizes and overall device scaling. Aggressive scaling of, e.g., a six transistor static random access memory (6T SRAM) cell, can be difficult with a SIT based FIN definition for a FINFET for 20 nanometer (nm) and 15 nm technology nodes and beyond, since the FIN pitch sets the SRAM cell size. Stated another way, the SRAM cell size is related to an integer multiple of the FIN pitch.
Lithography for such small devices can be extremely difficult. Restrictive design rules are required, and only a few patterns are feasible. A proposed solution has been to use unidirectional metal (metal that extends in a single direction, such as horizontally or vertically) for the metal 1 and metal 2 layers, instead of the conventional bidirectional metals, for both digital logic and SRAMs. However, at the extreme gate pitches or contact to poly pitch (CPP), gate shorts can occur.
A need therefore exists for efficient and cost effective methodology for producing SRAMs with good lithographic printability and reduced local interconnect to gate shorts, particularly for the 20 nm and 15 nm technology nodes, and beyond.